Design of 8-Bit Processor Element using Adiabatic Reversible Logic

Abstract

Low power design has become one of the primaries focuses in portable/embedded devices, where energy supplies are limited. To achieve low power consumption reversible logic becomes a competent technology where power dissipation becomes a limiting factor on performance. In modern VLSI (Very Large-Scale Integration), system power dissipation is very high due to rapid switching of internal signals. The complexity of VLSI circuits increases with miniaturization of integrated circuits every year due to packing more and more logic elements into smaller volumes. The reduction of power dissipation has become a crucial issue in today’s hardware design process. The foremost aim of this research is to develop a novel 8-bit processing element which supports 8-bit addition, subtraction and multiplication using a new 3-vector input and 3-vector output reversible gate named Modified Toffoli using Gate Diffusion Input technique (MTGDI). The power reduction in the processing element can be achieved by using adiabatic reversible logic. The logic technique deployed in developing this 3-to-3 reversible logic gate is Gate Diffusion Input Technique (GDI). The versatile features of this proposed gate produce optimum number of garbage outputs and quantum cost with compared to the existing counterpart. To achieve this aim two objectives have been fixed. The former goal defines the creation of 3-to-3 reversible logic gate using synthesizable GDI library and the latter goal defines the creation of results of MTGDI gates in terms of rise time, fall time and total delay will be fully furnished. The propagation delay is observed, and the average of propagation delay of the inputs has been reported as the total delay of the circuit. The power consumption has been measured for all the bit combinations and its average power has been reported as follows: The proposed design has achieved magnificent results in regards to the design 8-bit processor.